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Blog moved to https://blog.apdu.fr/

I moved my blog from https://ludovicrousseau.blogspot.com/ to https://blog.apdu.fr/ . Why? I wanted to move away from Blogger (owne...

Monday, March 25, 2019

PySCard 1.9.8 released

I just released a new version 1.9.8 of pyscard. PySCard is a python module adding smart cards support (PC/SC) to Python.

The PySCard project is available at:

Changes

1.9.8 (March 2018)

  • SmartcardException: store the PC/SC return code in hresult
  • CardMonitoring: stop the looping only if PCSC exited
  • setup: support build on OpenBSD, and other BSD
  • Fix Windows 10 SCARD_E_SERVICE_STOPPED from SCardListReaders()
  • Minor documentation improvements

New version of pcsc-lite: 1.8.25

I just released a new version of pcsc-lite 1.8.25.
pcsc-lite is a Free Software implementation of the PC/SC (or WinSCard) API for Unix systems.

Changes
1.8.25: Ludovic Rousseau
25 March 2019
  • Fix a socket issue when pcscd is used inside LXC container
  • pcsc-spy: always provide a total time of execution
  • Fix resource leak if SCardEstablishContext() fails
  • Fix realloc(3) error handling (possible memory leak)
  • Remove usage of function chmod(2) to use fchmod(2) (fix race condition)

Sunday, March 17, 2019

ATR statistics: TA4

Article from the series "ATR statistics"

TA4

The first TA for T=15 encodes the clock stop indicator (X) and the class indicator (Y). The default values are X = "clock stop not supported" and Y = "only class A supported".

bits 8 and 7 indicate whether the card supports clock stop (≠ 00) or not (= 00) and, when supported, which state is preferred on the electrical circuit CLK when the clock is stopped.
  • 00b: Clock stop not supported
  • 01b: State L
  • 10b: State H
  • 11b: No preference

bits 6 to 1 indicate the classes of operating conditions accepted by the card. Each bit represents a class: bit 1 for class A, bit 2 for class B and bit 3 for class C.
  • 00 0001b: A only
  • 00 0010b: B only
  • 00 0100b: C only
  • 00 0011b: A and B
  • 00 0110b: B and C
  • 00 0111b: A, B and C
  • Any other value: RFU

TA4#%
200996.96 %
0x03271.30 %
0x83150.72 %
0xC3120.58 %
0x0760.29 %
0x4320.10 %
0xC710.05 %



Clock stop#%
not supported3352.38 %
state L23.17 %
state H1523.81 %
no preference1320.63 %

The class defines the current voltage the card can use:
  • class A: 5 V
  • class B: 3 V
  • class C: 1.8 V
Some readers can't provide a tension of 5V. For example the Gemalto CT1100 reader does only provide 3 V. The default value for TA4 is "only class A supported". Some (old) cards require a voltage of 5 V to work and will not work with a CT1100. That can be surprising.

Class#%
A & B5688.89 %
A & B & C711.11 %

ATR statistics: TD3 - Structural, encodes Y4 and T

Article from the series "ATR statistics"

TD3 - Structural, encodes Y4 and T

The ISO 7816-3 specification is not public. So I can't copy/paste part of the text. I will use Wikipedia instead.

Refer to TD1 - Structural, encodes Y2 and T since the definition of TD3 is identical to TD1.

TD3#%
200996.96 %
0x1F612.94 %
0x3F20.10 %



TD3 (as the other TDi bytes) is structural and indicates:
  • How to interpret the other ATR bytes
  • What communication protocol the card wants to use

For 96.96% of the ATRs no TD3 is present. So no other TA4, TB4, TC4 or TD4 is present and no new protocol is defined so the protocol(s) defined by TD1 and TD2 will be used.

For 2.94% of the ATRs TD3 = 0x1F. The high nibble is 0001b so TA4 is present and T=15 protocol is defined. One such ATR is 3B 94 18 81 B1 80 7D 1F 03 19 C8 00 50 DC.

For 0.10% of the ATRs TD3 = 0x3F. The high nibble is 0001b so TA4 and TB4 are present and T=15 protocol is defined. One such ATR is 3B DE 18 FF 81 F1 FE 43 00 3F 07 83 44 45 53 46 69 72 65 38 20 53 41 4D 2D 58 17.

ATR statistics: TC3

Article from the series "ATR statistics".

TC3

The ISO 7816-3 specification is not public. So I can't copy/paste part of the text. I will use Wikipedia instead.

For T = 1: type of error detection code used

Bit 1 of the first TC for T=1 indicates the error detection code to be used:
  • CRC if bit 1 is set to 1;
  • LRC (default value) if bit 1 is set to 0.
Bits 8 to 2 of the first TC for T=1 are reserved for future use and shall be set to 0.

TC3#%
201797.35 %
0x00552.65 %

In my list of ATR the only redundancy code used if LRC. I found no card using CRC.

LRC is the default algorithm. But 55 cards explicitly set it. I have no explanation for that.