Saturday, April 2, 2016

ATR statistics: TA1 - Global, encodes Fi and Di

Article from the series "ATR statistics"

TA1 - Global, encodes Fi and Di

The ISO 7816-3 specification is not public. So I can't copy/paste part of the text. I will use Wikipedia instead.

From Wikipedia https://en.wikipedia.org/wiki/Answer_to_reset#Interface_byte_TA1 (with some edition to remove extra details):
Interface byte TA1, if present, is global, and encodes the maximum clock frequency fmax supported by the card, and the number of clock periods per ETU that it suggests to use after the ATR, expressed as the ratio Fi/Di of two integers. When TA1 is absent, it's assumed default value is ‘11’, corresponding to fmax = 5 MHz, Fi = 372, Di = 1.

The 4 low-order bits of TA1 (4th MSbit to 1st LSbit) encode Di as:
4th to 1st bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Di RFU 1 2 4 8 16 32 64 12 20 RFU RFU RFU RFU RFU RFU

The 4 high-order bits of TA1 (8th MSbit to 5th LSbit) encode fmax and Fi as:
8th to 5th bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Fi 372 372 558 744 1 116 1 488 1 860 RFU RFU 512 768 1 024 1 536 2 048 RFU RFU
fmax (MHz) 4 5 6 8 12 16 20 5 7.5 10 15 20

TA1#%
93244.98 %
0x1824111.63 %
0x962029.75 %
0x941678.06 %
0x951587.63 %
0x131366.56 %
0x111245.98 %
0x00180.87 %
0x91160.77 %
0x12150.72 %
0x98150.72 %
0x14140.68 %
0x2180.39 %
0x1570.34 %
0x9760.29 %
0x3840.19 %
0x0110.05 %
0x0410.05 %
0x1610.05 %
0x3210.05 %
0x3610.05 %
0x3F10.05 %
0xA810.05 %
0xD610.05 %
0xFF10.05 %


The TA1 value indicates the maximal communication speed between the card and the reader supported by the card. The reader may not support such a high speed. A lower speed will then be used (negotiated by the reader itself or by the reader driver).

Data rate (communication speed)

To know the speed value we need to convert the TA1 value in Fi/Di into a speed value in bit/s.

TA1FiDicycles/ETUbits/s at 4 MhzFmax Mhzbits/s at Fmax
0x01372137210752410752
0x0437284686956486956
0x1637232113636365454545
0x32744237210752821505
0x3674432231739138347826
0x3F744RFURFURFURFURFU
0xA87681264625007.5117187.5
0xD6204832646250020312500
0xFFRFURFURFURFURFURFU
0x387441262645168129032
0x975126485000005625000
0x1537216231739135217391
0x2155815587168610752
0x14372846869565108695
0x12372218621505526881
0x985121242952385119047
0x915121512781259765
0x00372RFURFURFURFURFU
0x11372137210752513440
0x1337249343010553763
0x9551216321250005156250
0x9451286462500578125
0x9651232162500005312500
0x1837212311290325161290
0x11372137210752513440

The table provides the data rate value for a clock of 4 Mhz. We have seen in "CCID descriptor statistics: dwDefaultClock" that 4 Mhz is the default clock of 48% of the CCID readers in my list.

You can note that there is different values of Fi and Di that give the same data rate. For example TA1=0xA8 and TA1=0xD6 both give a data rate of 62500 bits/s when using a clock at 4 MHz.

Population

We can count the number of ATR for each value of TA1. We get the table bellow:
TA1bits/s at 4 Mhzbits/s at Fmax#
0x0110752107521
0x0486956869561
0x163636364545451
0x3210752215051
0x361739133478261
0x3FRFURFU1
0xA862500117187.51
0xD6625003125001
0xFFRFURFU1
0x38645161290324
0x975000006250006
0x151739132173917
0x217168107528
0x148695610869514
0x12215052688115
0x989523811904715
0x917812976516
0x00RFURFU18
0x111075213440124
0x134301053763136
0x95125000156250158
0x946250078125167
0x96250000312500202
0x18129032161290241
1075213440932

We can draw a graph of the number of ATR for a given data rates to get an idea of the repartition:

In the graph I merged the results for a same data rate. So for the value 10 752 bits/s we get the sum of TA1=0x11 and no TA1 so the default value of 0x11. The total is then 932+124=1056.

We can also compute and display the median value:

Half of the cards have a data rate below 86 956 bits/s and the other half has a data rate above 86 956 bits/s.

Using Fmax

The Fi value also gives the maximal clock speed supported by the smart card. The value goes from 4 Mhz to 20 MHz. If we reuse the same examples the maximal clock speed for TA1=0xA8 is 7.5 Mhz and for TA1=0xD6 it is 20 Mhz. The data rates using the maximal clock speed are then quiet different: we have 11 7187.5 bits/s for TA1=0xA8 and 312 500 bits/s for TA1=0xD6.

So we get another distribution graph:

And another median:

This time the median value is 113 871 bits/s.

Reader max clock speed

Note that only 4 readers have a clock that can go up to 20 Mhz (or more). But I guess they are bogus readers.
The highest "common" clock speed is more likely 16 Mhz with 16 readers (3.95%).